Generating Functional Delay Fault Tests for Non-scan Sequential Circuits

The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. These fault models form one joint functional fault model. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the length of clock sequence. The length of clock sequence is determined using the presented functional fault models. The experimental results demonstrate the superiority of the delay test patterns generated at the functional level using the introduced functional fault models against the transition test patterns obtained at the gate level by deterministic test pattern generator. The functional delay test generation method especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.